synplify.tcl 1.62 KB
Newer Older
Christian Fibich's avatar
Christian Fibich committed
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
history clear
project -new tinyvga_fiji.prj
impl -add hx8k
set_option -technology SBTiCE40
set_option -part iCE40HX8K
add_file tinyvga_fiji.prj
add_file ../../fiji/tinyvga_constraints.synplify.fdc

add_file -vhdl ../../fiji/tinyvga_wrapper.vhd
add_file -vhdl ../../fiji/tinyvga_config_pkg.vhd

add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_controller_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_controller_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_controller_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_top_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_top_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_top_struc.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_tx_buffer_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_tx_buffer_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_tx_buffer_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_uart_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_uart_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_uart_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_unit_.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_unit_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_injection_unit_rtl.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/fault_selection_type_pkg.vhd
add_file -vhdl $::env(FIJI_ROOT)/hw/rtl/private_config_pkg.vhd

set_option -top_module fiji_top
set_option -result_file hx8k/tinyvga_fiji.edf
set_option -result_format edif
set_option -write_verilog 1

project -save tinyvga_fiji.prj 
project -run