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# HX8K Demo for FIJI+Yosys #

## Prerequisites ##

* Yosys, Arachne-PNR, icepack
* (sadly) Synplify as the VHDL frontend
* FIJI (+environment variable `$FIJI_ROOT` pointing to the checked-out FIJI directory)
* Configuration of Synplify in `impl/instrumented/Makefile`

## FIJI Flow ##

1. Carry out the initial synthesis step to obtain a netlist & configure
   FIJI by executing

    $ make fiji-instrument

   in `impl/original`

2. Perform the second synthesis step by running

    $ make prog && make fiji-launch

   in `impl/instrumented`

3. Inject & observe faults using the FIJI EE GUI

## Non-FIJI Flow ##

To just implement & download the original hardware, just run

    $ make prog

in `impl/original`

## Simulation ##

To simulate the design for a few frames, run

    $ make

in `sim`. Not much automated checking done here...