README 645 Bytes
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1. Create a new Vivado post-synthesis project in the 'vivado' directory named 'basys3_test_1.xpr'
    

    Add Source: 
        ../synp/basys3/spriteflyer_top.vm as source

    Add Constraints files:
        ../fiji/tmr_vga_demo_constraints.vivado.xdc
        ../../../boards/pins_basys3.xdc
        ./pins_fiji.xdc
        ./clock.xdc

    The pin and clock constraints have already been added in this demo.
    In a 'real' flow, these would have to be manually transferred or
    entered.

   Set xc7a35tcpg236-1 as device

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   Set fiji_top as top-level module
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2. Check pin and clock constraints

3. Run implementation and generate bitstream