spriteflyer_top.prj 3.16 KB
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#--  Synopsys, Inc.
#--  Version J-2014.09-SP2
#--  Project file /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/fiji/basys3_test_1/synp/spriteflyer_top.prj

#project files
add_file -fpga_constraint "spriteflyer_top.fdc"
add_file -vhdl -lib work "../fiji/tmr_vga_demo_config_pkg.vhd"
add_file -vhdl -lib work "../fiji/tmr_vga_demo_wrapper.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_struc.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_selection_type_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/private_config_pkg.vhd"
add_file -structver "../fiji/tmr_vga_demo_instrumented.vm"
add_file -fpga_constraint "../fiji/tmr_vga_demo_constraints.synplify.fdc"



#implementation: "basys3"
impl -add basys3 -type fpga

#
#implementation attributes

set_option -vlog_std sysv
set_option -project_relative_includes 1

#par_1 attributes
set_option -job par_1 -add par

#device options
set_option -technology Artix7
set_option -part XC7A35T
set_option -package CPG236
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0

# mapper_options
set_option -frequency auto
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# xilinx_options
set_option -RWCheckOnRam 1

# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1

# Xilinx Artix7
set_option -use_vivado 1
set_option -enable_prepacking 1

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "basys3/spriteflyer_top.vm"
impl -active "basys3"