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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[<Signal Processing Hardware (Oscilloscope)] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage1[Stage 1 Front-End Impedance and Capacitance Matching>]
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= Research on existing solutions
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= Research on existing front-end solutions
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To gather more knowledge about how a typical oscilloscope performs analog-signal processing, the results of the state-of-the-art research (see xy) were further analyzed.
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For this purpose, only projects with access to the schematic of the hardware provided enough information.
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... | ... | @@ -73,4 +73,4 @@ The results of the analysis of the previously mentioned projects lead to the fin |
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>] |
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[<Signal Processing Hardware (Oscilloscope)] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage1[Stage 1 Front-End Impedance and Capacitance Matching>] |