Changes

Page history
rename oscilloscope hardware chapters and add content to sig_proc_osci_stage2.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
Hide whitespace changes
Inline Side-by-side
sig_proc_osci_hardware.asciidoc 0 → 100644
View page @ e9beebe5
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
= Signal Processing Hardware (Oscilloscope)
To enable the measurement of analog waveforms outside of the ADCs input voltage range, the measured signal has to pass several signal processing stages. +
The analog hardware prepares the signal for digitalization.
{empty} +
Figure 1 shows an overview of the front-end stages and is applied to both analog channels of the Signal-Toolkit.
{empty} +
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_overview.PNG[caption="Figure 1: ",title="Overview of the structural design of the OpenLab oscilloscope front-end",align="center"]
{empty} +
A detailed description of each stage will be given by the following sub-chapters.
{empty} +
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage1[Stage 1 Front-End Impedance and Capacitance Matching]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage2[Stage 2 Offset Compensation and Op-amp Input Stage]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage3[Stage 3 Variable Amplification]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage4[Stage 4 Adding a Constant Offset to the Signal]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage5[Stage 5 ADC Protection]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage6[Stage 6 Impedance converter]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage7[Stage 7 Trigger detection]
{empty} +
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]