sig_proc_osci_hardware.asciidoc

@@ -15,10 +15,11 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci
 
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-A detailed description of each stage will be given by the following sub-chapters.
+A detailed description of each stage, and the analysis of existing solutions, will be given by the following sub-chapters.
 
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+* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_research[Research on existing front-end solutions]
 * https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage1[Stage 1 Front-End Impedance and Capacitance Matching]
 * https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage2[Stage 2 Offset Compensation and Op-amp Input Stage]
 * https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage3[Stage 3 Variable Amplification]