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Updated table of content
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Feb 01, 2017
by
Patrick Schmitt
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@@ -23,3 +23,6 @@ https://es.technikum-wien.at/openlab/openlab_wiki/wikis/asciidoc_cheatsheet[Asci
.. https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_SETS[Sequential Equivalent Time Samling]
.. https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_RETS[Random Equivalent Time Samling]
. https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation]
.. https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_CONFIG[Configuring the FPGA design for capturing samples in SETS-mode]
.. https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_FLOW[The process of capturing and reconstructing waveforms during SETS-mode]
.. https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_COMPONENT[The implementation of the SETS component of the FPGA design]
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