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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
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= FPGA-based DE0
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The DE0 is a beginner friendly development kit for FPGA design, manufactured by Terasic [1].
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The FPGA of the DE0 is the Cyclon III by Altera [2]. It offers a total of 15.408 Logic Elements (LEs) which is enough for the respective application purpose regarding the OpenLab project.
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Figure 1 shows the front of the DE0 development board
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{empty} +
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== Detailed specification (taken from [1])
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* FPGA
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** Cyclone III 3C16 FPGA
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*** 15,408 LEs
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*** 56 M9K Embedded Memory Blocks
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*** 504K total RAM bits
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*** 56 embedded multipliers
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*** 4 PLLs
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*** 346 user I/O pins
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*** FineLine BGA 484-pin package
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* Memory
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** SDRAM
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*** One 8-Mbyte Single Data Rate Synchronous Dynamic RAM memory chip
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** Flash memory
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*** 4-Mbyte NOR Flash memory
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*** Support Byte (8-bits)/Word (16-bits) mode
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** SD card socket
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*** Provides both SPI and SD 1-bit mode SD Card access
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*Interface
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** Built-in USB Blaster circuit
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*** On-board USB Blaster for programming
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*** Using the Altera EPM240 CPLD
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** Altera Serial Configuration device
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*** Altera EPCS4 serial EEPROM chip
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** Pushbutton switches
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*** 3 pushbutton switches
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** Slide switches
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*** 10 Slide switches
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** General User Interfaces
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*** 10 Green color LEDs
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*** 4 seven-segment displays
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*** 16x2 LCD Interface (Not include LCD module)
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** Clock inputs
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*** 50-MHz oscillator
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** VGA output
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*** Uses a 4-bit resistor-network DAC
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*** With 15-pin high-density D-sub connector
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*** Supports up to 1280x1024 at 60-Hz refresh rate
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** Serial ports
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*** One RS-232 port (Without DB-9 serial connector)
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*** One PS/2 port (Can be used through a PS/2 Y Cable to allow you to connect a keyboard and mouse to one port)
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** Two 40-pin expansion headers
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*** 72 Cyclone III 3.3V I/O pins, as well as 8 power and ground lines, are brought out to two 40-pin expansion connectors
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*** 40-pin header is designed to accept a standard 40-pin ribbon cable used for IDE hard drives
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>] |