== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_SigGen_FPGA[<FPGA/CPLD-basd projects/products] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_RCL[State of the Art Research (RCCL-Multimeter)>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_SigGen_FPGA[<FPGA/CPLD-basd projects/products] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_RCL[State of the Art Research (RCL-Multimeter)>]
This section provides a closer look at the signal generators that performed best during the market
research and seemed most important.
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@@ -30,9 +30,26 @@ beginner students. In addition, the OpenLab Signal Generator
uses external hardware to increase the maximum output
voltage and enable offset generation.
== Soundkarten Oszillograph
Figure 2 shows a screenshot of the software signal generator solution from C.Zeitnitz. The
program also features an oscilloscope and a spectrum analyzer which are not depicted here.
It uses the LabView Runtime, hence its familiar look and feel. The channels are clearly separated
and can be controlled by knobs or text input. Apart from the standard waveforms, it also
supports generating signals through a formula. Channel 2 shows this configuration.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SOTA_siggen_sc/SOTA_siggen_sc_zeitnitz.png[caption="Figure 1: Screenshot of C. Zeitnits's signal generator (2)",title="",height=220,align="center"]
{empty} +
Although the signal generator has no preview window, the signal can be looped back internally
and seen in the oscilloscope window. As a whole, using the signal generator was perceived
quite intuitive and straightforward. For private and non-commercial use the application is free,
otherwise a license is required which costs about 10e per installation excl. VAT. Additional
hardware is not available.
== Others
* AF Signal Funktions Generator[3]
* Daqarta[4]
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@@ -50,4 +67,4 @@ The content of his chapter is taken from the master thesis "_Development of a So
{empty} +
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_SigGen_FPGA[<FPGA/CPLD-basd projects/products] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_RCL[State of the Art Research (RCCL-Multimeter)>]
\ No newline at end of file
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_SigGen_FPGA[<FPGA/CPLD-basd projects/products] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SOTA_RCL[State of the Art Research (RCL-Multimeter)>]
