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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
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= Sequential Equivalent Time Samling - Theory
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During this mode, the oscilloscope acquires one sample per trigger. Each sample is taken at a specific time which is synchronised by the trigger of the oscilloscope.
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Hence the trigger is the reference point of this ETS implementation. Figure 1 illustrates the process of capturing a signal using Sequential Equivalent Time Sampling (SETS).
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/ETS_SETS/ETS_SETS.JPG[caption="Figure 1: ",title="Illustration of the SETS procedure (1)",height=350,align="center"]
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As shown in figure 1, the oscilloscope takes the first sample of the input signal at the first detected trigger event.
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The oscilloscope now has to wait a specific time before the next sample can be taken. This time is depended on how fast the built-in ADCs are able to sample again.
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This time is illustrated in figure 1 as the Re-Arm Time. If the ADCs are armed again, the next sample will be taken after the following trigger event plus an additional delay.
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This delay will be incremented after each taken sample.
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The reconstruction of the waveform is done by combining the taken samples together. The intervals between each sample is exactly the same and represents the "virtual sample rate".
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The virtual sample rate is the sample rate which is achieved by using the ETS mode instead of real-time sampling.
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The ADCs of the oscilloscope are still sampling at their specified maximum sample rate. The higher rate, the virtual sample rate, is only achieved using ETS.
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== The implementation of ETS on the OpenLab oscilloscope, is based on this specific method. Some adjustments were done in order to achieve maximum performance.
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== Bibliography
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. _What is the difference between an equivalent time sampling oscilloscope and a real-time oscilloscope?_ Techn. Rep., Agilent Technologies, November 2013.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>] |