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SETS_theory.asciidoc
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[<Equivalent Time Sampling - theory] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
= Sequential Equivalent Time Samling - Theory
......@@ -7,7 +7,7 @@ Hence the trigger is the reference point of this ETS implementation. Figure 1 il
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/ETS_SETS/ETS_SETS.JPG[caption="Figure 1: ",title="Illustration of the SETS procedure (1)",height=350,align="center"]
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_theory/SETS_theory.JPG[caption="Figure 1: ",title="Illustration of the SETS procedure (1)",height=350,align="center"]
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......@@ -34,4 +34,4 @@ The ADCs of the oscilloscope are still sampling at their specified maximum sampl
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[<Equivalent Time Sampling - theory] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_FPGA[Sequential Equivalent Time Sampling - FPGA Implementation>]
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