Home | <Equivalent Time Sampling - Theory | Sequential Equivalent Time Sampling - FPGA Implementation>
During this mode, the oscilloscope acquires one sample per trigger. Each sample is taken at a specific time which is synchronised by the trigger of the oscilloscope. Hence the trigger is the reference point of this ETS implementation. Figure 1 illustrates the process of capturing a signal using Sequential Equivalent Time Sampling (SETS).
As shown in figure 1, the oscilloscope takes the first sample of the input signal at the first detected trigger event. The oscilloscope now has to wait a specific time before the next sample can be taken. This time is depended on how fast the built-in ADCs are able to sample again. This time is illustrated in figure 1 as the Re-Arm Time. If the ADCs are armed again, the next sample will be taken after the following trigger event plus an additional delay. This delay will be incremented after each taken sample.
The reconstruction of the waveform is done by combining the taken samples together. The intervals between each sample is exactly the same and represents the "virtual sample rate". The virtual sample rate is the sample rate which is achieved by using the ETS mode instead of real-time sampling. The ADCs of the oscilloscope are still sampling at their specified maximum sample rate. The higher rate, the virtual sample rate, is only achieved using ETS.
The implementation of ETS on the OpenLab oscilloscope, is based on this specific method. Some adjustments were done in order to achieve maximum performance.
What is the difference between an equivalent time sampling oscilloscope and a real-time oscilloscope? Techn. Rep., Agilent Technologies, November 2013.