... | @@ -131,8 +131,8 @@ This process is only valid while composing the first packet of one complete ETS |
... | @@ -131,8 +131,8 @@ This process is only valid while composing the first packet of one complete ETS |
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For the remaining packets, the FPGA has to delay the point in time at which the ADC captures the first sample.
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For the remaining packets, the FPGA has to delay the point in time at which the ADC captures the first sample.
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This delay is specified by the virtual sample rate which is determined by the GUI.
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This delay is specified by the virtual sample rate which is determined by the GUI.
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The delay indicates the time distance between two samples after complete reconstruction of the waveform.
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The delay indicates the time distance between two samples after complete reconstruction of the waveform. +
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For details see https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory] and https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[Sequential Equivalent Time Samling - Theory].
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For details see https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory] and https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[Sequential Equivalent Time Samling - Theory]. +
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Depending on the settings, send by the GUI, the FPGA has to set the delay value for further processing. The FPGA delays the ADC acquisition by counting cycles of its system clock.
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Depending on the settings, send by the GUI, the FPGA has to set the delay value for further processing. The FPGA delays the ADC acquisition by counting cycles of its system clock.
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{empty} +
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{empty} +
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