SETS_FPGA.asciidoc

@@ -187,8 +187,9 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SET
 
 {empty} +
 
-_T~del~_ represents the delay that the FPGA adds after the first ETS packet was completed.
-The third ETS packet will add _2T~del~_ as delay. The fourth _3T~del~_ and so on.
+_T~del~_ represents the delay that the FPGA adds after the first ETS packet was completed. +
+The third ETS packet will add _2T~del~_ as delay. +
+The fourth _3T~del~_ and so on.
 
 {empty} +