... | ... | @@ -187,8 +187,9 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SET |
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{empty} +
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_T~del~_ represents the delay that the FPGA adds after the first ETS packet was completed.
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The third ETS packet will add _2T~del~_ as delay. The fourth _3T~del~_ and so on.
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_T~del~_ represents the delay that the FPGA adds after the first ETS packet was completed. +
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The third ETS packet will add _2T~del~_ as delay. +
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The fourth _3T~del~_ and so on.
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{empty} +
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... | ... | |