SETS_FPGA.asciidoc

@@ -11,9 +11,12 @@ The following sections explains how a waveform is captured and displayed using t
 
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-* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_CONFIG[Configuring the FPGA design for capturing samples in SETS-mode]
-* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_FLOW[The process of capturing and reconstructing waveforms during SETS-mode]
-* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_FPGA_COMPONENT[The implementation of the SETS component of the FPGA design]
+To configure the FPGA design to acquire samples in SETS, the GUI has to send the necessary parameters using a protocol.
+This is done as soon as the user leaves the time base in which the ADCs are able to sample at real time.
+Because of the selected ADCs, the maximum real time sample rate is 2.5 MSa/s. This sample rate is used, if the user selects 20 μs/div as time base.
+A time base smaller than this will require a higher sample rate which is only achievable using the SETS mode.
+After receiving the necessary parameters from the GUI, the FPGA starts capturing the first samples of the measured signal.
+The process of capturing the first sample in relation to the timing behavior of the ADC is illustrated in Figure 1.
 
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