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Re-sized images in SETS_FPGA.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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...@@ -41,7 +41,7 @@ This process is shown in figure 1. ...@@ -41,7 +41,7 @@ This process is shown in figure 1.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ADC_power_down.JPG[caption="Figure 1: ",title="Timing details of the power-down process of the ADS7885 ADC (1)",height=350,align="center"] image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ADC_power_down.JPG[caption="Figure 1: ",title="Timing details of the power-down process of the ADS7885 ADC (1)",height=200,align="center"]
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...@@ -50,7 +50,7 @@ During warm-up the output of the ADC will be invalid. This process is illustrate ...@@ -50,7 +50,7 @@ During warm-up the output of the ADC will be invalid. This process is illustrate
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ADC_power_up.JPG[caption="Figure 2: ",title="Timing details of the power-up process of the ADS7885 ADC (1)",height=350,align="center"] image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ADC_power_up.JPG[caption="Figure 2: ",title="Timing details of the power-up process of the ADS7885 ADC (1)",height=200,align="center"]
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