... | ... | @@ -97,4 +97,8 @@ Because of the fact that the input signal has to be repetitive, the FPGA can cal |
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_formula1.png[caption="Formula 1: ",title="Calculates the timing to start the acquisition during the first SETS-packet",height=350,align="center"]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |