... | ... | @@ -148,7 +148,8 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG |
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^| Virtual Sample Rate
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^| Acquisition Rounds
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^| Time Distance Sample-Sample [ns]
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^| Time Distance Sample-Sample [FPGA Clock Cycles]
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^| Time Distance Sample-Sample
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[FPGA Clock Cycles]
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|5MSa/s
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|5MSa/s
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... | ... | |