SETS_FPGA.asciidoc

@@ -148,7 +148,8 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 ^| Virtual Sample Rate
 ^| Acquisition Rounds
 ^| Time Distance Sample-Sample [ns]
-^| Time Distance Sample-Sample [FPGA Clock Cycles]
+^| Time Distance Sample-Sample
+[FPGA Clock Cycles]
 
 |5MSa/s
 |5MSa/s