SETS_FPGA.asciidoc

@@ -13,7 +13,7 @@ The following sections explains how a waveform is captured and displayed using t
 
 == Activiating the SETS-mode
 
-To configure the FPGA design to acquire samples in SETS, the GUI has to send the necessary parameters using a protocol.
+To configure the FPGA design to acquire samples in SETS, the GUI has to send the necessary parameters using the OpenLab protocol.
 This is done as soon as the user leaves the time base in which the ADCs are able to sample at real time.
 Because of the selected ADCs, the maximum real time sample rate is 2.5 MSa/s. This sample rate is used, if the user selects 20 μs/div as time base.
 A time base smaller than this will require a higher sample rate which is only achievable using the SETS mode.