centering cells is not possible on the es.technikum-wien.at gitlab wiki server

SETS_FPGA.asciidoc

@@ -141,36 +141,16 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 
 {empty} +
 
-:frame: sides
-:grid: rows
-:halign: center
-:valign: middle
-
-.Table test
-[width="50%",options="header"]
-|====
-||frame | grid |valign |halign
-v| 
- 
- 
-|{frame} | {grid} |{valign} |{halign}
-|====
-
-[cols="^,^,^,^", options="header"]
-|====
-
-| Virtual Sample Rate
-| Acquisition Rounds
-| Time Distance Sample-Sample [ns]
-| Time Distance Sample-Sample
-  [FPGA Clock Cycles]
-
-| 5MSa/s
-| 5MSa/s
-| 5MSa/s
-| 5MSa/s
-
-|====
+.Table 1: Timing relations regarding the supported ETS sample rates
+[options="header"]
+|======================
+| 3+|*ETS FPGA-time settings*
+|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
+|5MSa/s |Item 2 |Item 3 |Item 4
+|5MSa/s |Item 2 |Item 3 |Item 4
+|5MSa/s |Item 2 |Item 3 |Item 4
+|5MSa/s |Item 2 |Item 3 |Item 4
+|======================
 
 
 == https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >