... | ... | @@ -141,36 +141,16 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG |
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.Table test
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|====
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| Virtual Sample Rate
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| Acquisition Rounds
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| Time Distance Sample-Sample [ns]
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| Time Distance Sample-Sample
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[FPGA Clock Cycles]
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| 5MSa/s
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| 5MSa/s
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| 5MSa/s
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| 5MSa/s
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|====
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.Table 1: Timing relations regarding the supported ETS sample rates
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[options="header"]
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|======================
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| 3+|*ETS FPGA-time settings*
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|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
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|5MSa/s |Item 2 |Item 3 |Item 4
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|5MSa/s |Item 2 |Item 3 |Item 4
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|5MSa/s |Item 2 |Item 3 |Item 4
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|5MSa/s |Item 2 |Item 3 |Item 4
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|======================
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |