SETS_FPGA.asciidoc

@@ -173,7 +173,7 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SET
 
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-The added delay is represented by _N~delay~_. Depending on the current packet number, a multiple of the delay is added to the calculation.
+The added delay is represented by _N~delay~_. Depending on the current packet number, a multiple of the delay is added to the calculation. +
 _ETS_RESOLUTION_ is the time distance between two samples and is represented in system clock cycles. (see table 1)
 
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