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updated SETS_FPGA.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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...@@ -97,7 +97,7 @@ Because of the fact that the input signal has to be repetitive, the FPGA can cal ...@@ -97,7 +97,7 @@ Because of the fact that the input signal has to be repetitive, the FPGA can cal
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_formula1.png[caption="Formula 1: ",title="Calculates the timing to start the acquisition during the first SETS-packet",height=150,align="center"] image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_formula1.png[caption="Formula 1: ",title="Calculates the timing to start the acquisition during the first SETS-packet",height=50,align="center"]
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