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resized image of table 1 in order to fix visual bugs
authored
Feb 02, 2017
by
Patrick Schmitt
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SETS_FPGA.asciidoc
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@@ -153,7 +153,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
//|======================
//Decided to insert an image of the table because asciidoc sucks
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table_bolt.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",
height=246,
align="center"]
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table_bolt
_small
.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",align="center"]
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