... | ... | @@ -153,7 +153,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG |
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//|======================
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//Decided to insert an image of the table because asciidoc sucks
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",height=250,align="center"]
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",height=230,align="center"]
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{empty} +
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... | ... | |