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added a new version of table 1 with thicker lines for better scaling
authored
Feb 02, 2017
by
Patrick Schmitt
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SETS_FPGA.asciidoc
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@@ -153,7 +153,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
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//Decided to insert an image of the table because asciidoc sucks
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",height=244,align="center"]
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table
_bolt
.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",height=244,align="center"]
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