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updated scaling of figure 5 in SETS_FPGA.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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......@@ -183,7 +183,7 @@ It highlights the differences between acquiring during the first ETS packet and
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ETS_ADC_afterfirst.png[caption="Figure 5: ",title="Capturing samples after the first acquisition round (ETS)",height=510,align="center"]
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ETS_ADC_afterfirst.png[caption="Figure 5: ",title="Capturing samples after the first acquisition round (ETS)",height=550,align="center"]
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