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At 50MSa/s virtual sample rate, the FPGA is not able to set the correct delay between two samples.
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This is due to the restrictions of the system clock timing. 50MSa/s would require a time distance between two samples of exactly 20ns.
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This value cannot be reached by a system clock of 120Mhz. So the FPGA is sampling at 60MSa/s at this case.
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This does not affect measurement quality. The signal is correctly reconstructed by the GUI.
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This delay, set by the GUI, is considered during the calculation of the ADC timing.
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The following calculations are valid for all ETS packets excluding the first packet.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |
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