At 50MSa/s virtual sample rate, the FPGA is not able to set the correct delay between two samples.
This is due to the restrictions of the system clock timing. 50MSa/s would require a time distance between two samples of exactly 20ns.
This value cannot be reached by a system clock of 120Mhz. So the FPGA is sampling at 60MSa/s at this case.
This does not affect measurement quality. The signal is correctly reconstructed by the GUI.
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This delay, set by the GUI, is considered during the calculation of the ADC timing.
The following calculations are valid for all ETS packets excluding the first packet.
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