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try to config table authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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...@@ -141,7 +141,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -141,7 +141,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
{empty} + {empty} +
.Table 1: Timing relations regarding the supported ETS sample rates
[width="40%",frame="topbot",options="header"] [width="40%",frame="topbot",options="header"]
|====================== |======================
| *ETS FPGA-time settings* | *ETS FPGA-time settings*
...@@ -151,6 +151,6 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -151,6 +151,6 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
|3 |Item 3 |3 |Item 3
|6 |Three items |6 |Three items
|====================== |======================
.Table 1: Timing relations regarding the supported ETS sample rates
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > == https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >