... | ... | @@ -85,6 +85,8 @@ If the FPGA would stop acquiring the input signal, the GUI won’t be able to re |
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== Calculating the timing information for pricesly control the acquisition during SETS-mode
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After the period of the input signal is analyzed and saved in form of the counter value, the FPGA continues with calculating the timing information in order to control the ADCs.
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According to the https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[Sequential Equivalent Time Samling - Theory],
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the first sample of the first ETS packet should be acquired at the same moment a trigger edge was detected. The ADS7885 ADC is not able to take one sample at a specific time.
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