SETS_FPGA.asciidoc

@@ -142,7 +142,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 {empty} +
 
 .Table 1: Timing relations regarding the supported ETS sample rates
-[width="50%",cols=">s,^2m,^2e",frame="topbot",options="header"]
+[cols=">s,^2m,^2e",frame="topbot",options="header"]
 |======================
 | 3+|*ETS FPGA-time settings*
 |Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]