updated content of SETS_FPGA.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
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The added delay is represented by _N~delay~_. Depending on the current packet number, a multiple of the delay is added to the calculation.
_ETS_RESOLUTION_ is the time distance between two samples and is represented in system clock cycles. (see table 1)
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >
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