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A time base smaller than this will require a higher sample rate which is only achievable using the SETS mode.
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After receiving the necessary parameters from the GUI, the FPGA has to collect additional information about the input signal.
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{empty} +
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== Analysing the input signal
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To determine the exact point in time at which the ADCs should be powered on, the period of the input signal has to be analyzed. This process is shown in figure 1.
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