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removed asciidoc table and inserted an image of the table authored by Patrick Schmitt's avatar Patrick Schmitt 
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SETS_FPGA.asciidoc
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...@@ -141,16 +141,20 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -141,16 +141,20 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
{empty} + {empty} +
.Table 1: Timing relations regarding the supported ETS sample rates //.Table 1: Timing relations regarding the supported ETS sample rates
[options="header"] //[options="header"]
|====================== //|======================
| 3+|*ETS FPGA-time settings* //| 3+|*ETS FPGA-time settings*
|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [Clock Cycles] //|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [Clock Cycles]
|5MSa/s |2 |200.0 |24 //|5MSa/s |2 |200.0 |24
|10MSa/s |4 |100.0 |12 //|10MSa/s |4 |100.0 |12
|20Sa/s |8 |50.0 |6 //|20Sa/s |8 |50.0 |6
|50MSa/s |20 |16.6 |2 //|50MSa/s |20 |16.6 |2
|====================== //|======================
//Decided to insert an image of the table because asciidoc sucks
image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_time_table.PNG[caption="Table 1: ",title="Timing relations regarding the supported ETS sample rates",height=445,align="center"]
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > {empty} +
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >
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