... | ... | @@ -120,7 +120,7 @@ The process of capturing the first sample in relation to the timing behaviour of |
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ETS_ADC_Timing.png[caption="Figure 4: ",title="Capturing samples during the first acquisition round (ETS)",height=450,align="center"]
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ETS_ADC_Timing.png[caption="Figure 4: ",title="Capturing samples during the first acquisition round (ETS)",height=445,align="center"]
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