... | ... | @@ -190,7 +190,15 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SET |
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_T~del~_ represents the delay that the FPGA adds after the first ETS packet was completed.
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The third ETS packet will add _2T~del~_ as delay. The fourth _3T~del~_ and so on. +
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There is one situation which requires additional calculation in order to correctly control the timing of the ADC.
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{empty} +
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Signals with a smaller period time than the wake-up time of the ADC needs a slightly different approach.
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For example if _SIGNAL_LEARNING_CNT_ = 50 then the FPGA will calculate _ADC_CYCLE_START_CNT_ = -30 which will be unprocessable.
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For example if _SIGNAL_LEARNING_CNT_ = 50 then the FPGA will calculate _ADC_CYCLE_START_CNT_ = -30 which will be unprocessable. +
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By constantly adding the period time of the signal to the result of the first calculation, the result will be positive at some point.
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If the result is finally above zero, the value is considered as new _SIGNAL_LEARNING_CNT_ value.
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At this point the process will continue like previously described.
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |
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