_T~del~_ represents the delay that the FPGA adds after the first ETS packet was completed.
The third ETS packet will add _2T~del~_ as delay. The fourth _3T~del~_ and so on. +
There is one situation which requires additional calculation in order to correctly control the timing of the ADC.
{empty} +
Signals with a smaller period time than the wake-up time of the ADC needs a slightly different approach.
For example if _SIGNAL_LEARNING_CNT_ = 50 then the FPGA will calculate _ADC_CYCLE_START_CNT_ = -30 which will be unprocessable.
For example if _SIGNAL_LEARNING_CNT_ = 50 then the FPGA will calculate _ADC_CYCLE_START_CNT_ = -30 which will be unprocessable. +
By constantly adding the period time of the signal to the result of the first calculation, the result will be positive at some point.
If the result is finally above zero, the value is considered as new _SIGNAL_LEARNING_CNT_ value.
At this point the process will continue like previously described.
{empty} +
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