_T~del~_ represents the delay that the FPGA adds after the first ETS packet was completed.
The third ETS packet will add _2T~del~_ as delay. The fourth _3T~del~_ and so on.
{empty} +
There is one situation which requires additional calculation in order to correctly control the timing of the ADC.
Signals with a smaller period time than the wake-up time of the ADC needs a slightly different approach.
For example if _SIGNAL_LEARNING_CNT_ = 50 then the FPGA will calculate _ADC_CYCLE_START_CNT_ = -30 which will be unprocessable.
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