... | ... | @@ -66,7 +66,7 @@ The start and stop timings of the signal-period counter is shown by the time-lin |
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_signal_analysis.png[caption="Figure 3: ",title="Period analysis of the input signal (ETS)",height=350,align="center"]
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_signal_analysis.png[caption="Figure 3: ",title="Period analysis of the input signal (ETS)",height=400,align="center"]
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