... | ... | @@ -15,9 +15,17 @@ To configure the FPGA design to acquire samples in SETS, the GUI has to send the |
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This is done as soon as the user leaves the time base in which the ADCs are able to sample at real time.
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Because of the selected ADCs, the maximum real time sample rate is 2.5 MSa/s. This sample rate is used, if the user selects 20 μs/div as time base.
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A time base smaller than this will require a higher sample rate which is only achievable using the SETS mode.
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After receiving the necessary parameters from the GUI, the FPGA starts capturing the first samples of the measured signal.
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The process of capturing the first sample in relation to the timing behavior of the ADC is illustrated in Figure 1.
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After receiving the necessary parameters from the GUI, the FPGA has to collect additional information about the input signal.
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To determine the exact point in time at which the ADCs should be powered on, the period of the input signal has to be analyzed. This process is shown in figure 1.
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The input signal is represented by the first-, the output of the comparator by the second signal graph.
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The start and stop timings of the signal-period counter is shown by the time-line at the bottom of figure 1.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_signal_analysis.png[caption="Figure 1: ",title="Period analysis of the input signal (ETS)",height=280,align="center"]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |