SETS_FPGA.asciidoc

@@ -146,10 +146,10 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 |======================
 | 3+|*ETS FPGA-time settings*
 |Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [Clock Cycles]
-|5MSa/s |Item 2 |Item 3 |Item 4
-|5MSa/s |Item 2 |Item 3 |Item 4
-|5MSa/s |Item 2 |Item 3 |Item 4
-|5MSa/s |Item 2 |Item 3 |Item 4
+|5MSa/s |2 |200.0 |24
+|10MSa/s |4 |100.0 |12
+|20Sa/s |8 |50.0 |6
+|50MSa/s |20 |16.6 |2
 |======================