... | ... | @@ -146,10 +146,10 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG |
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| 3+|*ETS FPGA-time settings*
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|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [Clock Cycles]
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|5MSa/s |Item 2 |Item 3 |Item 4
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|5MSa/s |Item 2 |Item 3 |Item 4
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|5MSa/s |Item 2 |Item 3 |Item 4
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|5MSa/s |Item 2 |Item 3 |Item 4
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|5MSa/s |2 |200.0 |24
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|10MSa/s |4 |100.0 |12
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|20Sa/s |8 |50.0 |6
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|50MSa/s |20 |16.6 |2
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