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updated table authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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...@@ -146,10 +146,10 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -146,10 +146,10 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
|====================== |======================
| 3+|*ETS FPGA-time settings* | 3+|*ETS FPGA-time settings*
|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [Clock Cycles] |Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [Clock Cycles]
|5MSa/s |Item 2 |Item 3 |Item 4 |5MSa/s |2 |200.0 |24
|5MSa/s |Item 2 |Item 3 |Item 4 |10MSa/s |4 |100.0 |12
|5MSa/s |Item 2 |Item 3 |Item 4 |20Sa/s |8 |50.0 |6
|5MSa/s |Item 2 |Item 3 |Item 4 |50MSa/s |20 |16.6 |2
|====================== |======================
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