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== Calculating the timing information for the precision control of the acquisition during SETS-mode
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== Calculating the timing information for the precision control of the acquisition
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After the period of the input signal is analyzed and saved in form of the counter value, the FPGA continues with calculating the timing information in order to control the ADCs.
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According to the https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[Sequential Equivalent Time Samling - Theory],
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