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try to config table authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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...@@ -142,14 +142,14 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -142,14 +142,14 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
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.Table 1: Timing relations regarding the supported ETS sample rates .Table 1: Timing relations regarding the supported ETS sample rates
[width="40%",frame="topbot",options="header"] [frame="topbot",options="header"]
|====================== |======================
| *ETS FPGA-time settings* | *ETS FPGA-time settings*
|Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles] |Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
|5MSa/s |Item 1 |5MSa/s |Item 2 |Item 3 |Item 4
|2 |Item 2 |5MSa/s |Item 2 |Item 3 |Item 4
|3 |Item 3 |5MSa/s |Item 2 |Item 3 |Item 4
|6 |Three items |5MSa/s |Item 2 |Item 3 |Item 4
|====================== |======================
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