SETS_FPGA.asciidoc

@@ -142,14 +142,14 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 {empty} +
 
 .Table 1: Timing relations regarding the supported ETS sample rates
-[width="40%",frame="topbot",options="header"]
+[frame="topbot",options="header"]
 |======================
 | *ETS FPGA-time settings*
 |Virtual Sample Rate |Acquisition Rounds |Time Distance Sample-Sample [ns] |Time Distance Sample-Sample [FPGA Clock Cycles]
-|5MSa/s        |Item 1
-|2        |Item 2
-|3        |Item 3
-|6        |Three items
+|5MSa/s |Item 2 |Item 3 |Item 4
+|5MSa/s |Item 2 |Item 3 |Item 4
+|5MSa/s |Item 2 |Item 3 |Item 4
+|5MSa/s |Item 2 |Item 3 |Item 4
 |======================