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try to config table authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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...@@ -142,8 +142,9 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -142,8 +142,9 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
{empty} + {empty} +
.Table 1: Timing relations regarding the supported ETS sample rates .Table 1: Timing relations regarding the supported ETS sample rates
[cols="4*", options="header"] [options="header"]
|====================== |====
^| *ETS FPGA-time settings* ^| *ETS FPGA-time settings*
^| Virtual Sample Rate ^| Virtual Sample Rate
...@@ -155,7 +156,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -155,7 +156,7 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
|5MSa/s |5MSa/s
|5MSa/s |5MSa/s
|5MSa/s |5MSa/s
|====================== |====
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > == https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet >