SETS_FPGA.asciidoc

@@ -142,19 +142,19 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
 {empty} +
 
 .Table 1: Timing relations regarding the supported ETS sample rates
-[cols="4", options="header"]
+[cols="^,^,^,^", options="header"]
 |====
 
-^| Virtual Sample Rate
-^| Acquisition Rounds
-^| Time Distance Sample-Sample [ns]
-^| Time Distance Sample-Sample
-[FPGA Clock Cycles]
+| Virtual Sample Rate
+| Acquisition Rounds
+| Time Distance Sample-Sample [ns]
+| Time Distance Sample-Sample
+  [FPGA Clock Cycles]
 
-|5MSa/s
-|5MSa/s
-|5MSa/s
-|5MSa/s
+| 5MSa/s
+| 5MSa/s
+| 5MSa/s
+| 5MSa/s
 
 |====