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try to fix table authored by Patrick Schmitt's avatar Patrick Schmitt
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SETS_FPGA.asciidoc
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...@@ -141,12 +141,13 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG ...@@ -141,12 +141,13 @@ Table 1 shows the possible settings and its relation to the delay set by the FPG
{empty} + {empty} +
:frame: all :frame: sides
:grid: all :grid: rows
:halign: left :halign: center
:valign: top :valign: middle
[options="header"] .Table test
[width="50%",options="header"]
|==== |====
||frame | grid |valign |halign ||frame | grid |valign |halign
v|  v| 
... ...
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